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| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2012-06-15 20:55:19 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-06-20 22:49:45 +0200 |
| commit | e87c46993e30e8fe2e7a0981a532abe8bba07e62 (patch) | |
| tree | a318dd87c8bf92ba4eba9abff1fd5a0b836722ac /Documentation/w1 | |
| parent | drm/i915: VLV VGA port only handles on & off, like PCH VGA (diff) | |
| download | linux-e87c46993e30e8fe2e7a0981a532abe8bba07e62.tar.xz linux-e87c46993e30e8fe2e7a0981a532abe8bba07e62.zip | |
agp/intel: allow cacheable and GDFT PTEs on ValleyView
The PTE format is similar to SNB, but we don't support an MLC and don't
need chipset flushing.
Note: I have my questions whether this is right, given that MLC died
for snb & ivb, that ivb has grown a L3$ cache instead (which vlv seems
to have, too) and that the LLC bit here isn't actually LLC, but just
means 'snoop cpu caches'.
But I plan to burn this all with the heat of a thousands suns in my
gtt rework, so who cares ;-)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Added note.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'Documentation/w1')
0 files changed, 0 insertions, 0 deletions