diff options
author | Jesper Nilsson <jespern@axis.com> | 2015-03-25 10:06:21 +0100 |
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committer | Jesper Nilsson <jespern@axis.com> | 2015-03-25 10:42:53 +0100 |
commit | 1eb1390bb21b1aa3b303627eb254296f097988cb (patch) | |
tree | 650429961485f9e610c3668bdb15e6cce41aa704 /Documentation | |
parent | CRIS: add Axis 88 board device tree (diff) | |
download | linux-1eb1390bb21b1aa3b303627eb254296f097988cb.tar.xz linux-1eb1390bb21b1aa3b303627eb254296f097988cb.zip |
Add binding documentation for CRIS
Only includes the devboard 88 (CRISv32) at the moment.
Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/cris/axis.txt | 9 | ||||
-rw-r--r-- | Documentation/devicetree/bindings/cris/boards.txt | 8 | ||||
-rw-r--r-- | Documentation/devicetree/bindings/cris/interrupts.txt | 23 |
3 files changed, 40 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/cris/axis.txt b/Documentation/devicetree/bindings/cris/axis.txt new file mode 100644 index 000000000000..d209ca2a47c0 --- /dev/null +++ b/Documentation/devicetree/bindings/cris/axis.txt @@ -0,0 +1,9 @@ +Axis Communications AB +ARTPEC series SoC Device Tree Bindings + + +CRISv32 based SoCs are ETRAX FS and ARTPEC-3: + + - compatible = "axis,crisv32"; + + diff --git a/Documentation/devicetree/bindings/cris/boards.txt b/Documentation/devicetree/bindings/cris/boards.txt new file mode 100644 index 000000000000..533dd273ccf7 --- /dev/null +++ b/Documentation/devicetree/bindings/cris/boards.txt @@ -0,0 +1,8 @@ +Boards based on the CRIS SoCs: + +Required root node properties: + - compatible = should be one or more of the following: + - "axis,dev88" - for Axis devboard 88 with ETRAX FS + +Optional: + diff --git a/Documentation/devicetree/bindings/cris/interrupts.txt b/Documentation/devicetree/bindings/cris/interrupts.txt new file mode 100644 index 000000000000..e8b123b0a5e6 --- /dev/null +++ b/Documentation/devicetree/bindings/cris/interrupts.txt @@ -0,0 +1,23 @@ +* CRISv32 Interrupt Controller + +Interrupt controller for the CRISv32 SoCs. + +Main node required properties: + +- compatible : should be: + "axis,crisv32-intc" +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The type shall be a <u32> and the value shall be 1. +- reg: physical base address and size of the intc registers map. + +Example: + + intc: interrupt-controller { + compatible = "axis,crisv32-intc"; + reg = <0xb001c000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + |