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| author | Ulrich Hecht <ulrich.hecht@gmail.com> | 2014-05-23 15:27:15 +0200 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2014-05-23 22:38:25 +0200 |
| commit | 1923ca92a618b6107d3a44b5c9f9360b104dcddb (patch) | |
| tree | 06e117aa8d9e4ea2d15c0d9a539be0d81e020863 /Documentation | |
| parent | clk: tegra: Initialize xusb clocks (diff) | |
| download | linux-1923ca92a618b6107d3a44b5c9f9360b104dcddb.tar.xz linux-1923ca92a618b6107d3a44b5c9f9360b104dcddb.zip | |
clk: shmobile: Add R8A7740-specific clock support
Driver for the R8A7740's clocks that are too specific to be supported by a
generic driver.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt new file mode 100644 index 000000000000..2c03302f86ed --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt @@ -0,0 +1,41 @@ +These bindings should be considered EXPERIMENTAL for now. + +* Renesas R8A7740 Clock Pulse Generator (CPG) + +The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs +and several fixed ratio and variable ratio dividers. + +Required Properties: + + - compatible: Must be "renesas,r8a7740-cpg-clocks" + + - reg: Base address and length of the memory resource used by the CPG + + - clocks: Reference to the three parent clocks + - #clock-cells: Must be 1 + - clock-output-names: The names of the clocks. Supported clocks are + "system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b", + "m1", "hp", "hpp", "usbp", "s", "zb", "m3", and "cp". + + - renesas,mode: board-specific settings of the MD_CK* bits + + +Example +------- + +cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7740-cpg-clocks"; + reg = <0xe6150000 0x10000>; + clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>; + #clock-cells = <1>; + clock-output-names = "system", "pllc0", "pllc1", + "pllc2", "r", + "usb24s", + "i", "zg", "b", "m1", "hp", + "hpp", "usbp", "s", "zb", "m3", + "cp"; +}; + +&cpg_clocks { + renesas,mode = <0x05>; +}; |