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author | Hiroshi DOYU <hdoyu@nvidia.com> | 2012-05-10 09:42:32 +0200 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2012-05-10 23:46:09 +0200 |
commit | af4681097b23fe9c63a03d774de7c742fa3a920e (patch) | |
tree | 326ef53d1fa28d46410896f866f5e4ff9ddf792e /Documentation | |
parent | ARM: tegra20: Add Tegra Memory Controller(MC) driver (diff) | |
download | linux-af4681097b23fe9c63a03d774de7c742fa3a920e.tar.xz linux-af4681097b23fe9c63a03d774de7c742fa3a920e.zip |
ARM: tegra30: Add Tegra Memory Controller(MC) driver
Tegra Memory Controller(MC) driver for Tegra30
Added to support MC General interrupts, mainly for IOMMU(SMMU).
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt new file mode 100644 index 000000000000..e47e73f612f4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt @@ -0,0 +1,18 @@ +NVIDIA Tegra30 MC(Memory Controller) + +Required properties: +- compatible : "nvidia,tegra30-mc" +- reg : Should contain 4 register ranges(address and length); see the + example below. Note that the MC registers are interleaved with the + SMMU registers, and hence must be represented as multiple ranges. +- interrupts : Should contain MC General interrupt. + +Example: + mc { + compatible = "nvidia,tegra30-mc"; + reg = <0x7000f000 0x010 + 0x7000f03c 0x1b4 + 0x7000f200 0x028 + 0x7000f284 0x17c>; + interrupts = <0 77 0x04>; + }; |