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authorCatalin Marinas <catalin.marinas@arm.com>2014-04-01 19:32:55 +0200
committerCatalin Marinas <catalin.marinas@arm.com>2014-04-08 12:45:08 +0200
commitebf81a938dade3b450eb11c57fa744cfac4b523f (patch)
treefb7c10fd49f9ee3a71a7d5c0620d3a6745a082ea /Documentation
parentarm64: Add missing Kconfig for CONFIG_STRICT_DEVMEM (diff)
downloadlinux-ebf81a938dade3b450eb11c57fa744cfac4b523f.tar.xz
linux-ebf81a938dade3b450eb11c57fa744cfac4b523f.zip
arm64: Fix DMA range invalidation for cache line unaligned buffers
If the buffer needing cache invalidation for inbound DMA does start or end on a cache line aligned address, we need to use the non-destructive clean&invalidate operation. This issue was introduced by commit 7363590d2c46 (arm64: Implement coherent DMA API based on swiotlb). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Jon Medhurst (Tixy) <tixy@linaro.org>
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