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authorChen-Yu Tsai <wens@csie.org>2014-11-26 08:16:52 +0100
committerMaxime Ripard <maxime.ripard@free-electrons.com>2014-12-21 23:51:37 +0100
commit7954dfaee386d45d6ec655e5153ad67edf311a56 (patch)
treec8ebbdba5b2e9d16782133b2e8ca3e0db683a87a /Documentation
parentclk: sunxi: Remove ahb1_sdram from sun6i/sun8i protected clocks list (diff)
downloadlinux-7954dfaee386d45d6ec655e5153ad67edf311a56.tar.xz
linux-7954dfaee386d45d6ec655e5153ad67edf311a56.zip
clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider
This patch unifies the sun6i AHB1 clock, originally supported with separate mux and divider clks. It also adds support for the pre-divider on the PLL6 input, thus allowing the clock to be muxed to PLL6 with proper clock rate calculation. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi.txt2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 67b2b99f2b33..9dc4f55a04ad 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -26,7 +26,7 @@ Required properties:
"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
- "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
+ "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80