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authorJason Cooper <jason@lakedaemon.net>2014-07-22 22:46:48 +0200
committerJason Cooper <jason@lakedaemon.net>2014-07-22 22:46:48 +0200
commitba3ec5780bba27819bbc4f669e6c77418a00f14b (patch)
treeeebf5055d0fee3360e7930759ab1b3712eea2407 /Documentation
parentARM: Kirkwood: Remove mach-kirkwood (diff)
parentclk: mvebu: extend clk-cpu for dynamic frequency scaling (diff)
downloadlinux-ba3ec5780bba27819bbc4f669e6c77418a00f14b.tar.xz
linux-ba3ec5780bba27819bbc4f669e6c77418a00f14b.zip
Merge branch 'mvebu/soc-cpufreq' into mvebu/soc
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt5
1 files changed, 3 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
index feb830130714..99c214660bdc 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
@@ -3,14 +3,15 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms
Required properties:
- compatible : shall be one of the following:
"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
-- reg : Address and length of the clock complex register set
+- reg : Address and length of the clock complex register set, followed
+ by address and length of the PMU DFS registers
- #clock-cells : should be set to 1.
- clocks : shall be the input parent clock phandle for the clock.
cpuclk: clock-complex@d0018700 {
#clock-cells = <1>;
compatible = "marvell,armada-xp-cpu-clock";
- reg = <0xd0018700 0xA0>;
+ reg = <0xd0018700 0xA0>, <0x1c054 0x10>;
clocks = <&coreclk 1>;
}