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authorPadmavathi Venna <padma.v@samsung.com>2015-01-13 12:27:42 +0100
committerSylwester Nawrocki <s.nawrocki@samsung.com>2015-01-15 15:18:51 +0100
commit9f930a39e135d370d17e7a1ab73ddebcfb896f98 (patch)
tree12340bca7d6811a19524f13f648fa3085e471fc8 /Documentation
parentclk: samsung: exynos7: add clocks for SPI block (diff)
downloadlinux-9f930a39e135d370d17e7a1ab73ddebcfb896f98.tar.xz
linux-9f930a39e135d370d17e7a1ab73ddebcfb896f98.zip
clk: samsung: exynos7: add clocks for audio block
Add required clk support for I2S, PCM and SPDIF. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Reviewed-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/clock/exynos7-clock.txt9
1 files changed, 9 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 9282f71830b4..6bf1e7493f61 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -35,6 +35,7 @@ Required Properties for Clock Controller:
- "samsung,exynos7-clock-fsys0"
- "samsung,exynos7-clock-fsys1"
- "samsung,exynos7-clock-mscl"
+ - "samsung,exynos7-clock-aud"
- reg: physical base address of the controller and the length of
memory mapped region.
@@ -54,6 +55,7 @@ Input clocks for top0 clock controller:
- dout_sclk_bus1_pll
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
+ - dout_sclk_aud_pll
Input clocks for top1 clock controller:
- fin_pll
@@ -82,6 +84,9 @@ Input clocks for peric1 clock controller:
- sclk_spi2
- sclk_spi3
- sclk_spi4
+ - sclk_i2s1
+ - sclk_pcm1
+ - sclk_spdif
Input clocks for peris clock controller:
- fin_pll
@@ -97,3 +102,7 @@ Input clocks for fsys1 clock controller:
- dout_aclk_fsys1_200
- dout_sclk_mmc0
- dout_sclk_mmc1
+
+Input clocks for aud clock controller:
+ - fin_pll
+ - fout_aud_pll