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| author | John Garry <john.garry@huawei.com> | 2016-01-25 19:47:01 +0100 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2016-02-24 03:27:02 +0100 |
| commit | 7d37d6b6b293c6a9da19978d5918b71ebc4fb2c9 (patch) | |
| tree | 3eb2a8f95aac0e6037f395b0869377a94e00f0da /Documentation | |
| parent | bnx2fc: bnx2fc_eh_abort(): fix wrong return code. (diff) | |
| download | linux-7d37d6b6b293c6a9da19978d5918b71ebc4fb2c9.tar.xz linux-7d37d6b6b293c6a9da19978d5918b71ebc4fb2c9.zip | |
devicetree: bindings: hisi_sas: add v2 HW bindings
Add the dt bindings for HiSi SAS controller v2 HW.
The main difference in the controller from dt perspective is
interrupts. The v2 controller does not have dedicated fatal and
broadcast interrupts - they are multiplexed on the channel interrupt.
Each SAS v2 controller can issue upto 64 commands (or connection
requests) on the system bus without waiting for a response - this is
know as am-max-transmissions. In hip06, sas controller #1 has a
limitation that it has to limit am-max-transmissions to 32 - this
limitation is due to chip system bus design. It is not anticipated that
any future chip incorporating v2 controller will have such a limitation.
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/scsi/hisilicon-sas.txt | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt index f67e761bcc18..bf2411f366e5 100644 --- a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt +++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt @@ -5,6 +5,7 @@ The HiSilicon SAS controller supports SAS/SATA. Main node required properties: - compatible : value should be as follows: (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset + (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset - sas-addr : array of 8 bytes for host SAS address - reg : Address and length of the SAS register - hisilicon,sas-syscon: phandle of syscon used for sas control @@ -13,7 +14,7 @@ Main node required properties: - ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg - queue-count : number of delivery and completion queues in the controller - phy-count : number of phys accessible by the controller - - interrupts : Interrupts for phys, completion queues, and fatal + - interrupts : For v1 hw: Interrupts for phys, completion queues, and fatal sources; the interrupts are ordered in 3 groups, as follows: - Phy interrupts - Completion queue interrupts @@ -30,6 +31,24 @@ Main node required properties: Fatal interrupts : the fatal interrupts are ordered as follows: - ECC - AXI bus + For v2 hw: Interrupts for phys, Sata, and completion queues; + the interrupts are ordered in 3 groups, as follows: + - Phy interrupts + - Sata interrupts + - Completion queue interrupts + Phy interrupts : Each controller has 2 phy interrupts: + - phy up/down + - channel interrupt + Sata interrupts : Each phy on the controller has 1 Sata + interrupt. The interrupts are ordered in increasing + order. + Completion queue interrupts : each completion queue has 1 + interrupt source. The interrupts are ordered in + increasing order. + +Optional main node properties: + - hip06-sas-v2-quirk-amt : when set, indicates that the v2 controller has the + "am-max-transmissions" limitation. Example: sas0: sas@c1000000 { |