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authorThor Thayer <tthayer@opensource.altera.com>2016-06-02 19:52:21 +0200
committerLee Jones <lee.jones@linaro.org>2016-11-29 09:21:18 +0100
commit7fff7d9b15449c317fcc5dcd82ebb17dd0ae53e1 (patch)
treea352e1f7db57d361acd557ebaf341dc46e6d6ccd /Documentation
parentmfd: arizona: Mark AIFx_TX_BCLK_RATE as readable for cs47l24 (diff)
downloadlinux-7fff7d9b15449c317fcc5dcd82ebb17dd0ae53e1.tar.xz
linux-7fff7d9b15449c317fcc5dcd82ebb17dd0ae53e1.zip
dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings
The Altera Arria10 Devkit System Resource chip is a Multi-Function Device with a GPIO expander. This patch adds documentation for the Altera A10-SR DT bindings. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat (limited to 'Documentation')
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diff --git a/Documentation/devicetree/bindings/mfd/altera-a10sr.txt b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt
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+* Altera Arria10 Development Kit System Resource Chip
+
+Required parent device properties:
+- compatible : "altr,a10sr"
+- spi-max-frequency : Maximum SPI frequency.
+- reg : The SPI Chip Select address for the Arria10
+ System Resource chip
+- interrupt-parent : The parent interrupt controller.
+- interrupts : The interrupt line the device is connected to.
+- interrupt-controller : Marks the device node as an interrupt controller.
+- #interrupt-cells : The number of cells to describe an IRQ, should be 2.
+ The first cell is the IRQ number.
+ The second cell is the flags, encoded as trigger
+ masks from ../interrupt-controller/interrupts.txt.
+
+The A10SR consists of these sub-devices:
+
+Device Description
+------ ----------
+a10sr_gpio GPIO Controller
+
+Arria10 GPIO
+Required Properties:
+- compatible : Should be "altr,a10sr-gpio"
+- gpio-controller : Marks the device node as a GPIO Controller.
+- #gpio-cells : Should be two. The first cell is the pin number and
+ the second cell is used to specify flags.
+ See ../gpio/gpio.txt for more information.
+
+Example:
+
+ resource-manager@0 {
+ compatible = "altr,a10sr";
+ reg = <0>;
+ spi-max-frequency = <100000>;
+ interrupt-parent = <&portb>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ a10sr_gpio: gpio-controller {
+ compatible = "altr,a10sr-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };