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| author | s.hauer@pengutronix.de <s.hauer@pengutronix.de> | 2008-04-25 12:56:04 +0200 |
|---|---|---|
| committer | Grant Likely <grant.likely@secretlab.ca> | 2008-04-29 15:16:59 +0200 |
| commit | 3cd2550c736688c7f2651134e08bd5b5db5bed70 (patch) | |
| tree | 1a018f08e0fdc0a036c77722ba05f3bb08add9eb /Documentation | |
| parent | [POWERPC] mpc5200: add interrupt type function (diff) | |
| download | linux-3cd2550c736688c7f2651134e08bd5b5db5bed70.tar.xz linux-3cd2550c736688c7f2651134e08bd5b5db5bed70.zip | |
[POWERPC] mpc5200: add gpiolib support for mpc5200
This patch adds gpiolib support for mpc5200 SOCs.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/powerpc/mpc52xx-device-tree-bindings.txt | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/Documentation/powerpc/mpc52xx-device-tree-bindings.txt b/Documentation/powerpc/mpc52xx-device-tree-bindings.txt index 5e03610e186f..cda7a7dffa6d 100644 --- a/Documentation/powerpc/mpc52xx-device-tree-bindings.txt +++ b/Documentation/powerpc/mpc52xx-device-tree-bindings.txt @@ -186,6 +186,12 @@ Recommended soc5200 child nodes; populate as needed for your board name device_type compatible Description ---- ----------- ---------- ----------- gpt@<addr> gpt fsl,mpc5200-gpt General purpose timers +gpt@<addr> gpt fsl,mpc5200-gpt-gpio General purpose + timers in GPIO mode +gpio@<addr> fsl,mpc5200-gpio MPC5200 simple gpio + controller +gpio@<addr> fsl,mpc5200-gpio-wkup MPC5200 wakeup gpio + controller rtc@<addr> rtc mpc5200-rtc Real time clock mscan@<addr> mscan mpc5200-mscan CAN bus controller pci@<addr> pci mpc5200-pci PCI bridge @@ -225,6 +231,12 @@ PSC in i2s mode: The mpc5200 and mpc5200b PSCs are not compatible when in i2s mode. An 'mpc5200b-psc-i2s' node cannot include 'mpc5200-psc-i2s' in the compatible field. +7) GPIO controller nodes +Each GPIO controller node should have the empty property gpio-controller and +#gpio-cells set to 2. First cell is the GPIO number which is interpreted +according to the bit numbers in the GPIO control registers. The second cell +is for flags which is currently unsused. + IV - Extra Notes ================ |