diff options
| author | Stefan Roese <sr@denx.de> | 2015-10-19 08:40:13 +0200 |
|---|---|---|
| committer | Brian Norris <computersforpeace@gmail.com> | 2015-10-26 21:19:40 +0100 |
| commit | e278fc71b2c63905d3631b8d7b12ab7bcba9d2be (patch) | |
| tree | 5560d7283e2ae7f9824d3b9ef725a803d9263f38 /Documentation | |
| parent | mtd: nand: vf610_nfc: use nand_check_erased_ecc_chunk() helper (diff) | |
| download | linux-e278fc71b2c63905d3631b8d7b12ab7bcba9d2be.tar.xz linux-e278fc71b2c63905d3631b8d7b12ab7bcba9d2be.zip | |
mtd: fsmc_nand: Add BCH4 SW ECC support for SPEAr600
This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
be used by boards equipped with a NAND chip that requires 4-bit ECC
strength. The SPEAr600 HW ECC only supports 1-bit ECC strength.
To enable SW BCH4, you need to specify this in your nand controller
DT node:
nand-ecc-mode = "soft_bch";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
Tested on a custom SPEAr600 board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
[Brian: tweaked the comments a bit]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/mtd/fsmc-nand.txt | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt index 5235cbc551b0..32636eb77304 100644 --- a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt +++ b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt @@ -30,6 +30,12 @@ Optional properties: command is asserted. Zero means one cycle, 255 means 256 cycles. - bank: default NAND bank to use (0-3 are valid, 0 is the default). +- nand-ecc-mode : see nand.txt +- nand-ecc-strength : see nand.txt +- nand-ecc-step-size : see nand.txt + +Can support 1-bit HW ECC (default) or if stronger correction is required, +software-based BCH. Example: |