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| author | Antoine Ténart <antoine.tenart@free-electrons.com> | 2017-06-15 16:43:25 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2017-06-16 18:27:13 +0200 |
| commit | e0f7ed8dd73806ae8ed9605c3e845c46c8d7712f (patch) | |
| tree | 8bc169fb395c27b179a126a562f50578b0abc897 /Documentation | |
| parent | net: mvmdio: simplify the smi read and write error paths (diff) | |
| download | linux-e0f7ed8dd73806ae8ed9605c3e845c46c8d7712f.tar.xz linux-e0f7ed8dd73806ae8ed9605c3e845c46c8d7712f.zip | |
dt-bindings: orion-mdio: document the new xmdio compatible
A new compatible for Marvell xMDIO interfaces was added into the Marvell
MDIO driver. Document this new compatible.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/net/marvell-orion-mdio.txt | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/net/marvell-orion-mdio.txt b/Documentation/devicetree/bindings/net/marvell-orion-mdio.txt index ccdabdcc8618..42cd81090a2c 100644 --- a/Documentation/devicetree/bindings/net/marvell-orion-mdio.txt +++ b/Documentation/devicetree/bindings/net/marvell-orion-mdio.txt @@ -1,12 +1,14 @@ * Marvell MDIO Ethernet Controller interface The Ethernet controllers of the Marvel Kirkwood, Dove, Orion5x, -MV78xx0, Armada 370 and Armada XP have an identical unit that provides -an interface with the MDIO bus. This driver handles this MDIO -interface. +MV78xx0, Armada 370, Armada XP, Armada 7k and Armada 8k have an +identical unit that provides an interface with the MDIO bus. +Additionally, Armada 7k and Armada 8k has a second unit which +provides an interface with the xMDIO bus. This driver handles +these interfaces. Required properties: -- compatible: "marvell,orion-mdio" +- compatible: "marvell,orion-mdio" or "marvell,xmdio" - reg: address and length of the MDIO registers. When an interrupt is not present, the length is the size of the SMI register (4 bytes) otherwise it must be 0x84 bytes to cover the interrupt control |