Merge tag 'edac_for_4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp

Pull EDAC updates from Borislav Petkov:

 - Stratix10 SDRAM support to altera_edac (Thor Thayer)

 - the usual misc fixes all over the place

[ Also, shared branch for socfpga_stratix10.dtsi file changes with the
  socfpga tree ]

* tag 'edac_for_4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp:
  EDAC, ghes: Make platform-based whitelisting x86-only
  EDAC, altera: Fix ARM64 build warning
  EDAC, skx: Fix skx_edac build error when ACPI_NFIT=m
  EDAC, ghes: Use BIT() macro
  EDAC, ghes: Add DDR4 and NVDIMM memory types
  EDAC, altera: Handle SDRAM Uncorrectable Errors on Stratix10
  Documentation: dt: edac: Move Altera SOCFPGA EDAC file
  EDAC, altera: Add support for Stratix10 SDRAM EDAC
  Documentation: dt: socfpga: Add Stratix10 ECC Manager binding
  EDAC, ghes: Remove unused argument to ghes_edac_report_mem_error()
  arm64: dts: stratix10: add sdram ecc
  EDAC, i7core: Fix spelling mistake: "redundacy" -> "redundancy"
  EDAC, ghes: Add a null pointer check in ghes_edac_unregister()
  ghes, EDAC: Fix ghes_edac registration
  arm64: dts: stratix10: Change pad skew values for EMAC0 PHY driver
  ARM: dts: consistently use 'atmel' as at24 manufacturer in cyclone5
  arm64: dts: stratix10: Add PL330 DMAC to Stratix10 dts
  arm64: dts: stratix10: enable i2c, add i2c periperals
  arm64: dts: stratix10: use clock bindings for the Stratix10 platform

1 files changed, 35 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
index 4a1714f96bab..5626560a6cfd 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
@@ -231,3 +231,38 @@ Example:
 				     <48 IRQ_TYPE_LEVEL_HIGH>;
 		};
 	};
+
+Stratix10 SoCFPGA ECC Manager
+The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
+in a shared register similar to the Arria10. However, ECC requires
+access to registers that can only be read from Secure Monitor with
+SMC calls. Therefore the device tree is slightly different.
+
+Required Properties:
+- compatible : Should be "altr,socfpga-s10-ecc-manager"
+- interrupts : Should be single bit error interrupt, then double bit error
+	interrupt.
+- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
+- #interrupt-cells : must be set to 2.
+
+Subcomponents:
+
+SDRAM ECC
+Required Properties:
+- compatible : Should be "altr,sdram-edac-s10"
+- interrupts : Should be single bit error interrupt, then double bit error
+	interrupt, in this order.
+
+Example:
+
+	eccmgr {
+		compatible = "altr,socfpga-s10-ecc-manager";
+		interrupts = <0 15 4>, <0 95 4>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		sdramedac {
+			compatible = "altr,sdram-edac-s10";
+			interrupts = <16 4>, <48 4>;
+		};
+	};