diff options
| author | Geert Uytterhoeven <geert@linux-m68k.org> | 2022-01-28 10:03:58 +0100 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2022-01-28 18:27:26 +0100 |
| commit | c89e5eb7dcf1519e5e084ee82e0d29d4e751ddb7 (patch) | |
| tree | 0c9eeb4366b130a2fea6f6d8c3251d49e2aac6b4 /Documentation | |
| parent | dt-bindings: interrupt-controller: sifive,plic: Fix number of interrupts (diff) | |
| download | linux-c89e5eb7dcf1519e5e084ee82e0d29d4e751ddb7.tar.xz linux-c89e5eb7dcf1519e5e084ee82e0d29d4e751ddb7.zip | |
dt-bindings: interrupt-controller: sifive,plic: Group interrupt tuples
To improve human readability and enable automatic validation, the tuples
in "interrupts-extended" properties should be grouped using angle
brackets.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/211705e74a2ce77de43d036c5dea032484119bf7.1643360419.git.geert@linux-m68k.org
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 5edaa08f576e..058997c4e3cd 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -90,12 +90,11 @@ examples: #interrupt-cells = <1>; compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; interrupt-controller; - interrupts-extended = < - &cpu0_intc 11 - &cpu1_intc 11 &cpu1_intc 9 - &cpu2_intc 11 &cpu2_intc 9 - &cpu3_intc 11 &cpu3_intc 9 - &cpu4_intc 11 &cpu4_intc 9>; + interrupts-extended = <&cpu0_intc 11>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>; reg = <0xc000000 0x4000000>; riscv,ndev = <10>; }; |