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author | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2018-05-14 22:04:54 +0200 |
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committer | David S. Miller <davem@davemloft.net> | 2018-05-15 22:41:14 +0200 |
commit | cd1436a26718b2c33a290e5db24d1507887626e6 (patch) | |
tree | 872741cf90fa23261e5e613ccdef6c7f4da0ffd4 /Documentation | |
parent | Merge branch 'sctp-Introduce-sctp_flush_ctx' (diff) | |
download | linux-cd1436a26718b2c33a290e5db24d1507887626e6.tar.xz linux-cd1436a26718b2c33a290e5db24d1507887626e6.zip |
dt-bindings: net: add DT bindings for Microsemi MIIM
DT bindings for the Microsemi MII Management Controller found on Microsemi
SoCs
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/net/mscc-miim.txt | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/net/mscc-miim.txt b/Documentation/devicetree/bindings/net/mscc-miim.txt new file mode 100644 index 000000000000..7104679cf59d --- /dev/null +++ b/Documentation/devicetree/bindings/net/mscc-miim.txt @@ -0,0 +1,26 @@ +Microsemi MII Management Controller (MIIM) / MDIO +================================================= + +Properties: +- compatible: must be "mscc,ocelot-miim" +- reg: The base address of the MDIO bus controller register bank. Optionally, a + second register bank can be defined if there is an associated reset register + for internal PHYs +- #address-cells: Must be <1>. +- #size-cells: Must be <0>. MDIO addresses have no size component. +- interrupts: interrupt specifier (refer to the interrupt binding) + +Typically an MDIO bus might have several children. + +Example: + mdio@107009c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,ocelot-miim"; + reg = <0x107009c 0x36>, <0x10700f0 0x8>; + interrupts = <14>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; |