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| author | Johan Jonker <jbx6244@gmail.com> | 2022-03-29 17:07:37 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2022-04-10 19:05:47 +0200 |
| commit | 04d3e427148f8ed7322f70e324731c81460671df (patch) | |
| tree | 14a067ad36615598d0b2929ecde3a5d2e607f7ae /Documentation | |
| parent | Linux 5.18-rc1 (diff) | |
| download | linux-04d3e427148f8ed7322f70e324731c81460671df.tar.xz linux-04d3e427148f8ed7322f70e324731c81460671df.zip | |
dt-bindings: clock: fix some conversion style issues for rockchip,rk3399-cru.yaml
With the conversion of rockchip,rk3399-cru.txt a table with external clocks
was copied. Make it a bit cleaner by aligning the columns. Also fix
a description. Phrases start with a capital.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220329150742.22093-1-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml index 72b286a1beba..76dd24d49a37 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml @@ -22,11 +22,11 @@ description: | There are several clocks that are generated outside the SoC. It is expected that they are defined using standard clock bindings with following clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "clkin_gmac" - external GMAC clock - optional, - - "clkin_i2s" - external I2S clock - optional, - - "pclkin_cif" - external ISP clock - optional, + - "xin24m" - crystal input - required, + - "xin32k" - rtc clock - optional, + - "clkin_gmac" - external GMAC clock - optional, + - "clkin_i2s" - external I2S clock - optional, + - "pclkin_cif" - external ISP clock - optional, - "clk_usbphy0_480m" - output clock of the pll in the usbphy0 - "clk_usbphy1_480m" - output clock of the pll in the usbphy1 @@ -62,8 +62,8 @@ properties: rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle - description: > - phandle to the syscon managing the "general register files". It is used + description: + Phandle to the syscon managing the "general register files". It is used for GRF muxes, if missing any muxes present in the GRF will not be available. |