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| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2022-03-12 00:49:36 +0100 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2022-04-08 13:35:21 +0200 |
| commit | 84f293b204ab1ef519278e7993e9930f03879627 (patch) | |
| tree | 2b7915e29d158de8b818d1dd3cef982a913c48ea /Documentation | |
| parent | dt-bindings: pci: layerscape-pci: Add a optional property big-endian (diff) | |
| download | linux-84f293b204ab1ef519278e7993e9930f03879627.tar.xz linux-84f293b204ab1ef519278e7993e9930f03879627.zip | |
dt-bindings: pci: layerscape-pci: Update the description of SCFG property
Update the description of the second entry of 'fsl,pcie-scfg' property,
as the LS1043A PCIe controller also has some control registers in SCFG
block, while it has 3 controllers.
Link: https://lore.kernel.org/r/20220311234938.8706-3-leoyang.li@nxp.com
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 215d2ee65c83..f1115fcd8088 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -34,7 +34,7 @@ Required properties: "intr": The interrupt that is asserted for controller interrupts - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node - The second entry must be '0' or '1' based on physical PCIe controller index. + The second entry is the physical PCIe controller index starting from '0'. This is used to get SCFG PEXN registers - dma-coherent: Indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software |