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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-05-21 11:55:17 +0200 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-05-21 11:55:17 +0200 |
| commit | 026d68be45a217f65f1617d08271f6838bfc07d7 (patch) | |
| tree | 8c85cbd8c0aeb7899473173fff41cd595a3401c6 /Documentation | |
| parent | Merge tag 'spi-v3.15-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/br... (diff) | |
| parent | clk: tegra: Fix wrong value written to PLLE_AUX (diff) | |
| download | linux-026d68be45a217f65f1617d08271f6838bfc07d7.tar.xz linux-026d68be45a217f65f1617d08271f6838bfc07d7.zip | |
Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework fixes from Mike Turquette:
"Clock framework and driver fixes, all of which fix user-visible
regressions.
As usual most fixes are for platform-specific clock drivers, but there
are also two fixes to the clk core after recent changes to the way
that clock unregistration is handled"
* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux:
clk: tegra: Fix wrong value written to PLLE_AUX
clk: shmobile: clk-mstp: change to using clock-indices
clk: Fix slab corruption in clk_unregister()
clk: Fix double free due to devm_clk_register()
clk: socfpga: fix clock driver for 3.15
clk: divider: Fix best div calculation for power-of-two and table dividers
clk: bcm281xx: don't use unnamed structs or unions
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt index 5992dceec7af..02a25d99ca61 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt @@ -43,7 +43,7 @@ Example clock-output-names = "tpu0", "mmcif1", "sdhi3", "sdhi2", "sdhi1", "sdhi0", "mmcif0"; - renesas,clock-indices = < + clock-indices = < R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 |