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| author | Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> | 2018-09-12 20:06:35 +0200 |
|---|---|---|
| committer | Andy Gross <andy.gross@linaro.org> | 2018-09-13 22:54:19 +0200 |
| commit | b54ef3814f4a30c4c023ea099c8e4c962cfe3614 (patch) | |
| tree | 544ae3fe489d779a7172b7e555cff4f6a90348b2 /Documentation | |
| parent | drivers: edac: Add EDAC driver support for QCOM SoCs (diff) | |
| download | linux-b54ef3814f4a30c4c023ea099c8e4c962cfe3614.tar.xz linux-b54ef3814f4a30c4c023ea099c8e4c962cfe3614.zip | |
dt-bindings: msm: Update documentation of qcom,llcc
Add reg-names and interrupts for LLCC documentation and the usage
examples. llcc broadcast base is added in addition to llcc base,
which is used for llcc broadcast writes.
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt index 5e85749262ae..eaee06b2d8f2 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt @@ -16,11 +16,26 @@ Properties: - reg: Usage: required Value Type: <prop-encoded-array> - Definition: Start address and the the size of the register region. + Definition: The first element specifies the llcc base start address and + the size of the register region. The second element specifies + the llcc broadcast base address and size of the register region. + +- reg-names: + Usage: required + Value Type: <stringlist> + Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base". + +- interrupts: + Usage: required + Definition: The interrupt is associated with the llcc edac device. + It's used for llcc cache single and double bit error detection + and reporting. Example: cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x250000>; + reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; |