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authorIcenowy Zheng <icenowy@aosc.io>2017-05-14 18:30:33 +0200
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-06-07 15:32:12 +0200
commited74f8a8a67952320277a53a0c46a0cdf44fbe8f (patch)
treeebfd2773e989842e5b457dc79f561cc04ccf1a69 /Documentation
parentclk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM (diff)
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dt-bindings: add binding for the Allwinner DE2 CCU
Allwinner "Display Engine 2.0" contains some clock controls in it. In order to add them as clock drivers, we need a device tree binding. Add the binding here. Also add the device tree binding headers. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/clock/sun8i-de2.txt31
1 files changed, 31 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
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index 000000000000..631d27cd89d6
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+++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
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+Allwinner Display Engine 2.0 Clock Control Binding
+--------------------------------------------------
+
+Required properties :
+- compatible: must contain one of the following compatibles:
+ - "allwinner,sun8i-a83t-de2-clk"
+ - "allwinner,sun8i-v3s-de2-clk"
+ - "allwinner,sun50i-h5-de2-clk"
+
+- reg: Must contain the registers base address and length
+- clocks: phandle to the clocks feeding the display engine subsystem.
+ Three are needed:
+ - "mod": the display engine module clock
+ - "bus": the bus clock for the whole display engine subsystem
+- clock-names: Must contain the clock names described just above
+- resets: phandle to the reset control for the display engine subsystem.
+- #clock-cells : must contain 1
+- #reset-cells : must contain 1
+
+Example:
+de2_clocks: clock@1000000 {
+ compatible = "allwinner,sun8i-a83t-de2-clk";
+ reg = <0x01000000 0x100000>;
+ clocks = <&ccu CLK_BUS_DE>,
+ <&ccu CLK_DE>;
+ clock-names = "bus",
+ "mod";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};