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| author | Chen-Yu Tsai <wens@csie.org> | 2014-09-16 12:04:01 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2014-09-27 09:05:43 +0200 |
| commit | 9c8176bfb67f98ed9a521b624dcb6ab7fa254aa7 (patch) | |
| tree | 52bf5988af67aa1c7423010c09dbccfe9ab40671 /Documentation | |
| parent | clk: sunxi: mod0: Introduce MMC proper phase handling (diff) | |
| download | linux-9c8176bfb67f98ed9a521b624dcb6ab7fa254aa7.tar.xz linux-9c8176bfb67f98ed9a521b624dcb6ab7fa254aa7.zip | |
clk: sunxi: Add sun8i MBUS clock support
The MBUS clock on sun8i is slightly different from the old mod0 clocks.
The divider is 3 bits wider, while also needing a divider table for the
higher 4 values, which all set the same divider.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/sunxi.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index eb690ed92a53..ed116df9c3e7 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -50,6 +50,7 @@ Required properties: "allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10 "allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10 "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks + "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23 "allwinner,sun7i-a20-out-clk" - for the external output clocks "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31 "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 |