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authorSachin Kamat <sachin.kamat@linaro.org>2013-07-12 05:23:43 +0200
committerMike Turquette <mturquette@linaro.org>2013-08-09 00:57:18 +0200
commit6f9a4894c435bc9919dab31d90f69167d4638997 (patch)
tree979b8cc593b7e32821f5b5e30d13f2c8915e5bc6 /Documentation
parentclk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC (diff)
downloadlinux-6f9a4894c435bc9919dab31d90f69167d4638997.tar.xz
linux-6f9a4894c435bc9919dab31d90f69167d4638997.zip
Documentation: clk: Fix a trivial typo in audss
Fixes a trivial typo. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/clock/clk-exynos-audss.txt2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index a1201802f90d..75e2e1999f87 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -2,7 +2,7 @@
The Samsung Audio Subsystem clock controller generates and supplies clocks
to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
-binding described here is applicable to all SoC's in Exynos family.
+binding described here is applicable to all SoCs in Exynos family.
Required Properties: