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author | Will Deacon <will@kernel.org> | 2022-12-06 11:44:07 +0100 |
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committer | Will Deacon <will@kernel.org> | 2022-12-06 11:44:07 +0100 |
commit | 9f930478c648d25e3a4c3db3d69a65cf05ff939a (patch) | |
tree | 8ab71a9c8c3522c7f1727b374e6aeb7b60120dea /Documentation | |
parent | Merge branch 'for-next/asm-const' into for-next/core (diff) | |
parent | kselftest/arm64: Add SVE 2.1 to hwcap test (diff) | |
download | linux-9f930478c648d25e3a4c3db3d69a65cf05ff939a.tar.xz linux-9f930478c648d25e3a4c3db3d69a65cf05ff939a.zip |
Merge branch 'for-next/cpufeature' into for-next/core
* for-next/cpufeature:
kselftest/arm64: Add SVE 2.1 to hwcap test
arm64/hwcap: Add support for SVE 2.1
kselftest/arm64: Add FEAT_RPRFM to the hwcap test
arm64/hwcap: Add support for FEAT_RPRFM
kselftest/arm64: Add FEAT_CSSC to the hwcap selftest
arm64/hwcap: Add support for FEAT_CSSC
arm64: Enable data independent timing (DIT) in the kernel
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/arm64/elf_hwcaps.rst | 9 | ||||
-rw-r--r-- | Documentation/arm64/sve.rst | 1 |
2 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst index bb34287c8e01..6fed84f935df 100644 --- a/Documentation/arm64/elf_hwcaps.rst +++ b/Documentation/arm64/elf_hwcaps.rst @@ -275,6 +275,15 @@ HWCAP2_EBF16 HWCAP2_SVE_EBF16 Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0010. +HWCAP2_CSSC + Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0001. + +HWCAP2_RPRFM + Functionality implied by ID_AA64ISAR2_EL1.RPRFM == 0b0001. + +HWCAP2_SVE2P1 + Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0010. + 4. Unused AT_HWCAP bits ----------------------- diff --git a/Documentation/arm64/sve.rst b/Documentation/arm64/sve.rst index f338ee2df46d..c7a356bf4e8f 100644 --- a/Documentation/arm64/sve.rst +++ b/Documentation/arm64/sve.rst @@ -52,6 +52,7 @@ model features for SVE is included in Appendix A. HWCAP2_SVEBITPERM HWCAP2_SVESHA3 HWCAP2_SVESM4 + HWCAP2_SVE2P1 This list may be extended over time as the SVE architecture evolves. |