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| author | Heiko Stuebner <heiko.stuebner@theobroma-systems.com> | 2019-12-16 13:24:47 +0100 |
|---|---|---|
| committer | Kishon Vijay Abraham I <kishon@ti.com> | 2020-01-08 08:28:06 +0100 |
| commit | cb18b9a92b0baaa3188d67d1371079c1eacb3454 (patch) | |
| tree | e6aafdaaa35b099690ec14d1d97268ecdd3458f4 /Documentation | |
| parent | phy: lantiq: vrx200-pcie: Remove unneeded semicolon (diff) | |
| download | linux-cb18b9a92b0baaa3188d67d1371079c1eacb3454.tar.xz linux-cb18b9a92b0baaa3188d67d1371079c1eacb3454.zip | |
dt-bindings: phy: drop #clock-cells from rockchip,px30-dsi-dphy
Further review of the dsi components for the px30 revealed that the
phy shouldn't expose the pll as clock but instead handle settings
via phy parameters.
As the phy binding is new and not used anywhere yet, just drop them
so they don't get used.
Fixes: 3817c7961179 ("dt-bindings: phy: add yaml binding for rockchip,px30-dsi-dphy")
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml index bb0da87bcd84..476c56a1dc8c 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml @@ -13,9 +13,6 @@ properties: "#phy-cells": const: 0 - "#clock-cells": - const: 0 - compatible: enum: - rockchip,px30-dsi-dphy @@ -49,7 +46,6 @@ properties: required: - "#phy-cells" - - "#clock-cells" - compatible - reg - clocks @@ -66,7 +62,6 @@ examples: reg = <0x0 0xff2e0000 0x0 0x10000>; clocks = <&pmucru 13>, <&cru 12>; clock-names = "ref", "pclk"; - #clock-cells = <0>; resets = <&cru 12>; reset-names = "apb"; #phy-cells = <0>; |