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authorJaehoon Chung <jh80.chung@samsung.com>2014-02-14 13:27:09 +0100
committerChris Ball <chris@printf.net>2014-02-22 19:51:14 +0100
commit321bd41de1580f953c637de0fd81e06fcba8b3e8 (patch)
tree2a994c9ede622e29fce650b90351cd4f16d91893 /Documentation
parentmmc: core: Add DT bindings for eMMC high-speed DDR 1.8/1.2V (diff)
downloadlinux-321bd41de1580f953c637de0fd81e06fcba8b3e8.tar.xz
linux-321bd41de1580f953c637de0fd81e06fcba8b3e8.zip
mmc: core: Add DT bindings for eMMC HS200 1.8/1.2V
Provide the option to configure these speed modes per host, for those host driver's that can't distinguish this in runtime. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/mmc/mmc.txt2
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt
index 519d9523a413..9dce540771fb 100644
--- a/Documentation/devicetree/bindings/mmc/mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/mmc.txt
@@ -36,6 +36,8 @@ Optional properties:
- full-pwr-cycle: full power cycle of the card is supported
- mmc-highspeed-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported
- mmc-highspeed-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported
+- mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported
+- mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported
*NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
polarity properties, we have to fix the meaning of the "normal" and "inverted"