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| author | WANG Xuerui <git@xen0n.name> | 2023-01-09 02:35:11 +0100 |
|---|---|---|
| committer | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2023-01-24 00:35:54 +0100 |
| commit | 473a8ce756fdbd6e9fc0ffbf3ceb88394058763e (patch) | |
| tree | 9f7cbcd60aed37fcb7dc5cf447e9c820af96d5be /Documentation | |
| parent | rtc: brcmstb-waketimer: rename irq to wake_irq (diff) | |
| download | linux-473a8ce756fdbd6e9fc0ffbf3ceb88394058763e.tar.xz linux-473a8ce756fdbd6e9fc0ffbf3ceb88394058763e.zip | |
dt-bindings: rtc: Add Loongson LS2X RTC support
Document the binding for the LS2X RTC block found on the Loongson-2K SoC
and the LS7A bridge, originally appearing on the Loongson-2H.
Signed-off-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/0288efeb4209e4a49af07de6399045aaa00a970c.1673227292.git.zhoubinbin@loongson.cn
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/rtc/trivial-rtc.yaml | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml b/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml index d9fc120c61cc..0ef1ffd54655 100644 --- a/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml @@ -47,6 +47,8 @@ properties: - isil,isl1218 # Intersil ISL12022 Real-time Clock - isil,isl12022 + # Loongson-2K Socs/LS7A bridge Real-time Clock + - loongson,ls2x-rtc # Real Time Clock Module with I2C-Bus - microcrystal,rv3028 # Real Time Clock Module with I2C-Bus |