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authorJerome Brunet <jbrunet@baylibre.com>2018-12-03 18:16:38 +0100
committerKevin Hilman <khilman@baylibre.com>2018-12-05 02:04:39 +0100
commitfa3abfb6943ef2976deda78d83788a1352963f47 (patch)
tree8b390962cb6c5b60be398c28890b1d27bc776fa4 /Documentation
parentarm64: dts: meson-axg: remove alternate xtal (diff)
downloadlinux-fa3abfb6943ef2976deda78d83788a1352963f47.tar.xz
linux-fa3abfb6943ef2976deda78d83788a1352963f47.zip
dt-bindings: clk: meson: add ao controller clock inputs
Add the clock inputs of amlogic AO clock controller Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt10
1 files changed, 9 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
index 3a880528030e..79511d7bb321 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
@@ -11,6 +11,13 @@ Required Properties:
- GXM (S912) : "amlogic,meson-gxm-aoclkc"
- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
followed by the common "amlogic,meson-gx-aoclkc"
+- clocks: list of clock phandle, one for each entry clock-names.
+- clock-names: should contain the following:
+ * "xtal" : the platform xtal
+ * "mpeg-clk" : the main clock controller mother clock (aka clk81)
+ * "ext-32k-0" : external 32kHz reference #0 if any (optional)
+ * "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only)
+ * "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only)
- #clock-cells: should be 1.
@@ -40,8 +47,9 @@ ao_sysctrl: sys-ctrl@0 {
compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
#clock-cells = <1>;
#reset-cells = <1>;
+ clocks = <&xtal>, <&clkc CLKID_CLK81>;
+ clock-names = "xtal", "mpeg-clk";
};
-};
Example: UART controller node that consumes the clock and reset generated
by the clock controller: