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authorVince Weaver <vince@deater.net>2009-07-08 23:46:14 +0200
committerIngo Molnar <mingo@elte.hu>2009-07-10 10:28:26 +0200
commit11d1578f9454159c43499d1d8fe8a7d728c176a3 (patch)
tree2ad986dad1482083c1f61632f851883791d70aea /MAINTAINERS
parentperf_counter tools: Rename cache events to remove $ (diff)
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perf_counter: Add P6 PMU support
Add basic P6 PMU support. The P6 uses the EVNTSEL0 EN bit to enable/disable both its counters. We use this for the global enable/disable, and clear all config bits (except EN) to disable individual counters. Actual ia32 hardware doesn't support lfence, so use a locked op without side-effect to implement a full barrier. perf stat and perf record seem to function correctly. [a.p.zijlstra@chello.nl: cleanups and complete the enable/disable code] Signed-off-by: Vince Weaver <vince@deater.net> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <Pine.LNX.4.64.0907081718450.2715@pianoman.cluster.toy> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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