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| author | Anson Huang <Anson.Huang@nxp.com> | 2018-01-08 03:04:51 +0100 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2018-01-10 01:14:21 +0100 |
| commit | 5028f5d2b38ea68531d6b265b64e1741a141a828 (patch) | |
| tree | 2c4c1752fa091763575e300efa9510b104758486 /MAINTAINERS | |
| parent | ARM: dts: imx6ul: add 696MHz operating point (diff) | |
| download | linux-5028f5d2b38ea68531d6b265b64e1741a141a828.tar.xz linux-5028f5d2b38ea68531d6b265b64e1741a141a828.zip | |
cpufreq: imx6q: add 696MHz operating point for i.mx6ul
Add 696MHz operating point for i.MX6UL, only for those
parts with speed grading fuse set to 2b'10 supports
696MHz operating point, so, speed grading check is also
added for i.MX6UL in this patch, the clock tree for each
operating point are as below:
696MHz:
pll1 696000000
pll1_bypass 696000000
pll1_sys 696000000
pll1_sw 696000000
arm 696000000
528MHz:
pll2 528000000
pll2_bypass 528000000
pll2_bus 528000000
ca7_secondary_sel 528000000
step 528000000
pll1_sw 528000000
arm 528000000
396MHz:
pll2_pfd2_396m 396000000
ca7_secondary_sel 396000000
step 396000000
pll1_sw 396000000
arm 396000000
198MHz:
pll2_pfd2_396m 396000000
ca7_secondary_sel 396000000
step 396000000
pll1_sw 396000000
arm 198000000
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'MAINTAINERS')
0 files changed, 0 insertions, 0 deletions