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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2023-03-30 13:16:30 +0200 |
|---|---|---|
| committer | Lee Jones <lee@kernel.org> | 2023-04-26 12:40:35 +0200 |
| commit | 0be8907359df4c62319f5cb2c6981ff0d9ebf35a (patch) | |
| tree | 2d03f6a7a0213fe1d98cffd7e8d694d2815ca3b5 /MAINTAINERS | |
| parent | Documentation: ABI: sysfs-bus-counter: add cascade_counts_enable and external... (diff) | |
| download | linux-0be8907359df4c62319f5cb2c6981ff0d9ebf35a.tar.xz linux-0be8907359df4c62319f5cb2c6981ff0d9ebf35a.zip | |
counter: Add Renesas RZ/G2L MTU3a counter driver
Add RZ/G2L MTU3a counter driver. This IP supports the following
phase counting modes on MTU1 and MTU2 channels
1) 16-bit phase counting modes on MTU1 and MTU2 channels.
2) 32-bit phase counting mode by cascading MTU1 and MTU2 channels.
This patch adds 3 counter value channels.
count0: 16-bit phase counter value channel on MTU1
count1: 16-bit phase counter value channel on MTU2
count2: 32-bit phase counter value channel by cascading
MTU1 and MTU2 channels.
The external input phase clock pin for the counter value channels
are as follows:
count0: "MTCLKA-MTCLKB"
count1: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD"
count2: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD"
Use the sysfs variable "external_input_phase_clock_select" to select the
external input phase clock pin and "cascade_counts_enable" to enable/
disable cascading of channels.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: William Breathitt Gray <william.gray@linaro.org>
Acked-by: William Breathitt Gray <william.gray@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20230330111632.169434-5-biju.das.jz@bp.renesas.com
Diffstat (limited to 'MAINTAINERS')
0 files changed, 0 insertions, 0 deletions