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authorJakub Kicinski <kuba@kernel.org>2023-05-25 07:14:29 +0200
committerJakub Kicinski <kuba@kernel.org>2023-05-25 07:14:29 +0200
commitaa015a204b6094f909ee9863cd41e50b426dea7d (patch)
tree4de9cba4c997973f7f159e813bf2f95498e012da /MAINTAINERS
parentMerge branch 'bug-fixes-for-net-handshake' (diff)
parentnet: phy: mscc: enable VSC8501/2 RGMII RX clock (diff)
downloadlinux-aa015a204b6094f909ee9863cd41e50b426dea7d.tar.xz
linux-aa015a204b6094f909ee9863cd41e50b426dea7d.zip
Merge branch 'net-phy-mscc-support-vsc8501'
David Epping says: ==================== net: phy: mscc: support VSC8501 this updated series of patches adds support for the VSC8501 Ethernet PHY and fixes support for the VSC8502 PHY in cases where no other software (like U-Boot) has initialized the PHY after power up. The first patch simply adds the VSC8502 to the MODULE_DEVICE_TABLE, where I guess it was unintentionally missing. I have no hardware to test my change. The second patch adds the VSC8501 PHY with exactly the same driver implementation as the existing VSC8502. The (new) third patch removes phydev locking from vsc85xx_rgmii_set_skews(), as discussed for v2 of the patch set. The (now) fourth patch fixes the initialization for VSC8501 and VSC8502. I have tested this patch with VSC8501 on hardware in RGMII mode only. https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/VSC8501-03_Datasheet_60001741A.PDF https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/VSC8502-03_Datasheet_60001742B.pdf Table 4-42 "RGMII CONTROL, ADDRESS 20E2 (0X14)" Bit 11 for each of them. By default the RX_CLK is disabled for these PHYs. In cases where no other software, like U-Boot, enabled the clock, this results in no received packets being handed to the MAC. The patch enables this clock output. According to Microchip support (case number 01268776) this applies to all modes (RGMII, GMII, and MII). Other PHYs sharing the same register map and code, like VSC8530/31/40/41 have the clock enabled and the relevant bit 11 is reserved and read-only for them. As per previous discussion the patch still clears the bit on these PHYs, too, possibly more easily supporting other future PHYs implementing this functionality. For the VSC8572 family of PHYs, having a different register map, no such changes are applied. ==================== Link: https://lore.kernel.org/r/20230523153108.18548-1-david.epping@missinglinkelectronics.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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