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| author | Alex Helms <alexander.helms.jy@renesas.com> | 2022-09-12 20:36:13 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-10-01 02:34:35 +0200 |
| commit | 48c5e98fedd9e0b164df4de592fd740537ead9e2 (patch) | |
| tree | fff3052e2ae08d04e60d8e87671dcb990e4b8d3d /MAINTAINERS | |
| parent | dt-bindings: Renesas versaclock7 device tree bindings (diff) | |
| download | linux-48c5e98fedd9e0b164df4de592fd740537ead9e2.tar.xz linux-48c5e98fedd9e0b164df4de592fd740537ead9e2.zip | |
clk: Renesas versaclock7 ccf device driver
Renesas Versaclock7 is a family of configurable clock generator ICs
with fractional and integer dividers. This driver has basic support
for the RC21008A device, a clock synthesizer with a crystal input and
8 outputs. The supports changing the FOD and IOD rates, and each
output can be gated.
Signed-off-by: Alex Helms <alexander.helms.jy@renesas.com>
Link: https://lore.kernel.org/r/20220912183613.22213-3-alexander.helms.jy@renesas.com
Tested-by: Saeed Nowshadi <saeed.nowshadi@amd.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index c1b1c7ead11d..9bebe0165404 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17445,6 +17445,7 @@ RENESAS VERSACLOCK 7 CLOCK DRIVER M: Alex Helms <alexander.helms.jy@renesas.com> S: Maintained F: Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml +F: drivers/clk/clk-versaclock7.c RESET CONTROLLER FRAMEWORK M: Philipp Zabel <p.zabel@pengutronix.de> |