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authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>2017-06-21 21:16:26 +0200
committerStephen Boyd <sboyd@codeaurora.org>2017-07-17 20:50:59 +0200
commit6d7489c74a6ed73b4751b58b56c247bedd780a78 (patch)
tree158dbdd8dd805a4c4726b5cf72874197f202d5db /MAINTAINERS
parentLinux v4.13-rc1 (diff)
downloadlinux-6d7489c74a6ed73b4751b58b56c247bedd780a78.tar.xz
linux-6d7489c74a6ed73b4751b58b56c247bedd780a78.zip
clk: axs10x: introduce AXS10X pll driver
AXS10X boards manages it's clocks using various PLLs. These PLL has same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs. Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed using these dividers. We add pre-defined tables with supported rate values and appropriate configurations of IDIV, FBDIV and ODIV for each value. As of today we add support for PLLs that generate clock for the following devices: * ARC core on AXC CPU tiles. * ARC PGU on ARC SDP Mainboard. and more to come later. By this patch we add support for two plls (arc core pll and pgu pll), so we had to use two different init types: CLK_OF_DECLARE for arc core pll and regular probing for pgu pll. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Signed-off-by: Jose Abreu <joabreu@synopsys.com> [sboyd@codeaurora.org: Silence dubious !x & y sparse warning, make of_axs10x_pll_clk_setup() unregister clk on failure] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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diff --git a/MAINTAINERS b/MAINTAINERS
index 205d3977ac46..c571fcf62740 100644
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+++ b/MAINTAINERS
@@ -12745,6 +12745,12 @@ F: arch/arc/plat-axs10x
F: arch/arc/boot/dts/ax*
F: Documentation/devicetree/bindings/arc/axs10*
+SYNOPSYS ARC SDP clock driver
+M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+S: Supported
+F: drivers/clk/axs10x/*
+F: Documentation/devicetree/bindings/clock/snps,pll-clock.txt
+
SYSTEM CONFIGURATION (SYSCON)
M: Lee Jones <lee.jones@linaro.org>
M: Arnd Bergmann <arnd@arndb.de>