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authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>2017-08-25 19:39:14 +0200
committerStephen Boyd <sboyd@codeaurora.org>2017-08-31 07:36:05 +0200
commitdaeeb438c052e3763617c636943e07a8f3684e9e (patch)
tree5db2bde1740022066098ae70919e7a14093a4e22 /MAINTAINERS
parentclk: zte: constify clk_div_table (diff)
downloadlinux-daeeb438c052e3763617c636943e07a8f3684e9e.tar.xz
linux-daeeb438c052e3763617c636943e07a8f3684e9e.zip
ARC: clk: introduce HSDK pll driver
HSDK board manages its clocks using various PLLs. These PLL have same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs. Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed using these dividers. We add pre-defined tables with supported rate values and appropriate configurations of IDIV, FBDIV and ODIV for each value. As of today we add support for PLLs that generate clock for the HSDK arc cpus, system, ddr, AXI tunnel and hdmi. By this patch we add support for several plls (arc cpus pll and others), so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll and regular probing for others plls. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'MAINTAINERS')
-rw-r--r--MAINTAINERS6
1 files changed, 6 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index c571fcf62740..cf704c7df2f0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12738,6 +12738,12 @@ F: drivers/clocksource/arc_timer.c
F: drivers/tty/serial/arc_uart.c
T: git git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git
+SYNOPSYS ARC HSDK SDP pll clock driver
+M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+S: Supported
+F: drivers/clk/clk-hsdk-pll.c
+F: Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt
+
SYNOPSYS ARC SDP platform support
M: Alexey Brodkin <abrodkin@synopsys.com>
S: Supported