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| author | Conor Dooley <conor.dooley@microchip.com> | 2022-09-09 14:31:14 +0200 |
|---|---|---|
| committer | Claudiu Beznea <claudiu.beznea@microchip.com> | 2022-09-14 09:55:17 +0200 |
| commit | 05f9e36370c1517c8e03325f38910fd7ad30b177 (patch) | |
| tree | 6c6cd9ece38ac2269ea65b12d851086c569a0fc1 /README | |
| parent | clk: microchip: mpfs: add reset controller (diff) | |
| download | linux-05f9e36370c1517c8e03325f38910fd7ad30b177.tar.xz linux-05f9e36370c1517c8e03325f38910fd7ad30b177.zip | |
reset: add polarfire soc reset support
Add support for the resets on Microchip's PolarFire SoC (MPFS).
Reset control is a single register, wedged in between registers for
clock control. To fit with existed DT etc, the reset controller is
created using the aux device framework & set up in the clock driver.
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-6-conor.dooley@microchip.com
Diffstat (limited to 'README')
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