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author | James Morris <jmorris@namei.org> | 2008-08-28 02:47:34 +0200 |
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committer | James Morris <jmorris@namei.org> | 2008-08-28 02:47:34 +0200 |
commit | 86d688984deefa3ae5a802880c11f2b408b5d6cf (patch) | |
tree | 7ea5e8189b0a774626d3ed7c3c87df2495a4c4a0 /arch/alpha/include/asm/cache.h | |
parent | selinux: add support for installing a dummy policy (v2) (diff) | |
parent | IB/mlx4: Actually return L_Key and R_Key for fast register MRs (diff) | |
download | linux-86d688984deefa3ae5a802880c11f2b408b5d6cf.tar.xz linux-86d688984deefa3ae5a802880c11f2b408b5d6cf.zip |
Merge branch 'master' into next
Diffstat (limited to 'arch/alpha/include/asm/cache.h')
-rw-r--r-- | arch/alpha/include/asm/cache.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/alpha/include/asm/cache.h b/arch/alpha/include/asm/cache.h new file mode 100644 index 000000000000..f199e69a5d0b --- /dev/null +++ b/arch/alpha/include/asm/cache.h @@ -0,0 +1,23 @@ +/* + * include/asm-alpha/cache.h + */ +#ifndef __ARCH_ALPHA_CACHE_H +#define __ARCH_ALPHA_CACHE_H + + +/* Bytes per L1 (data) cache line. */ +#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EV6) +# define L1_CACHE_BYTES 64 +# define L1_CACHE_SHIFT 6 +#else +/* Both EV4 and EV5 are write-through, read-allocate, + direct-mapped, physical. +*/ +# define L1_CACHE_BYTES 32 +# define L1_CACHE_SHIFT 5 +#endif + +#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) +#define SMP_CACHE_BYTES L1_CACHE_BYTES + +#endif |