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authorTony Luck <tony.luck@intel.com>2012-07-19 20:28:46 +0200
committerIngo Molnar <mingo@kernel.org>2012-07-26 15:05:47 +0200
commit61b0fccd7f114573f973dfe25d864608822dc09e (patch)
tree8ba7f8a8d984cba1ae1c1a528e96309e6a73cd2a /arch/alpha
parentx86/mce: Move MCACOD defines from mce-severity.c to <asm/mce.h> (diff)
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x86/mce: Add quirk for instruction recovery on Sandy Bridge processors
Sandy Bridge processors follow the SDM (Vol 3B, Table 15-20) and set both the RIPV and EIPV bits in the MCG_STATUS register to zero for machine checks during instruction fetch. This is more than a little counter-intuitive and means that Linux cannot recover from these errors. Rather than insert special case code at several places in mce.c and mce-severity.c, we pretend the EIPV bit was set for just this case early in processing the machine check. Acked-by: Borislav Petkov <bp@amd64.org> Signed-off-by: Tony Luck <tony.luck@intel.com> Cc: Chen Gong <gong.chen@linux.intel.com> Cc: Huang Ying <ying.huang@intel.com> Cc: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Link: http://lkml.kernel.org/r/180a06f3f357cf9f78259ae443a082b14a29535b.1343078495.git.tony.luck@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/alpha')
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