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| author | Thomas Gleixner <tglx@linutronix.de> | 2016-06-03 15:05:51 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2016-06-03 15:05:51 +0200 |
| commit | 2eec3707a33fbf1c2e0a88ffc9fc0e465c2a59fd (patch) | |
| tree | 9e47763ecd38f0ddd29f07e1ce199680304449fa /arch/arc/boot/dts/nsim_700.dts | |
| parent | genirq: Fix missing return value in irq_destroy_ipi() (diff) | |
| parent | irqchip/irq-pic32-evic: Fix bug with external interrupts. (diff) | |
| download | linux-2eec3707a33fbf1c2e0a88ffc9fc0e465c2a59fd.tar.xz linux-2eec3707a33fbf1c2e0a88ffc9fc0e465c2a59fd.zip | |
Merge tag 'irqchip-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent
Merge irqchip updates from Marc Zyngier:
- A number of embarassing buglets (GICv3, PIC32)
- A more substential errata workaround for Cavium's GICv3 ITS
(kept for post-rc1 due to its dependency on NUMA)
Diffstat (limited to 'arch/arc/boot/dts/nsim_700.dts')
| -rw-r--r-- | arch/arc/boot/dts/nsim_700.dts | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arc/boot/dts/nsim_700.dts b/arch/arc/boot/dts/nsim_700.dts index 105a0017023f..5d5e373e0ebc 100644 --- a/arch/arc/boot/dts/nsim_700.dts +++ b/arch/arc/boot/dts/nsim_700.dts @@ -14,7 +14,7 @@ clock-frequency = <80000000>; /* 80 MHZ */ #address-cells = <1>; #size-cells = <1>; - interrupt-parent = <&intc>; + interrupt-parent = <&core_intc>; chosen { bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8"; @@ -32,7 +32,13 @@ /* child and parent address space 1:1 mapped */ ranges; - intc: interrupt-controller { + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <80000000>; + }; + + core_intc: interrupt-controller { compatible = "snps,arc700-intc"; interrupt-controller; #interrupt-cells = <1>; |