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| author | Vineet Gupta <vgupta@synopsys.com> | 2015-04-06 13:53:57 +0200 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2015-06-22 10:36:55 +0200 |
| commit | d1f317d8254413447bcd6b6adbde24a985d256c2 (patch) | |
| tree | 4b0ba3c3a5335e844edbf97403c12b88b04f69d5 /arch/arc/include/asm/cache.h | |
| parent | ARCv2: MMUv4: TLB programming Model changes (diff) | |
| download | linux-d1f317d8254413447bcd6b6adbde24a985d256c2.tar.xz linux-d1f317d8254413447bcd6b6adbde24a985d256c2.zip | |
ARCv2: MMUv4: cache programming model changes
Caveats about cache flush on ARCv2 based cores
- dcache is PIPT so paddr is sufficient for cache maintenance ops (no
need to setup PTAG reg
- icache is still VIPT but only aliasing configs need PTAG setup
So basically this is departure from MMU-v3 which always need vaddr in
line ops registers (DC_IVDL, DC_FLDL, IC_IVIL) but paddr in DC_PTAG,
IC_PTAG respectively.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/include/asm/cache.h')
| -rw-r--r-- | arch/arc/include/asm/cache.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 7861255da32d..e54977a7d006 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -82,4 +82,7 @@ extern void read_decode_cache_bcr(void); #define DC_CTRL_INV_MODE_FLUSH 0x40 #define DC_CTRL_FLUSH_STATUS 0x100 +/*System-level cache (L2 cache) related Auxiliary registers */ +#define ARC_REG_SLC_CFG 0x901 + #endif /* _ASM_CACHE_H */ |