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authorVineet Gupta <vgupta@synopsys.com>2016-10-01 01:13:28 +0200
committerVineet Gupta <vgupta@synopsys.com>2016-12-14 18:23:46 +0100
commit107177b14d8179f864315fc4daed9da777ed30c2 (patch)
treebf549522914db856961b39e9e12e3fc8654db3d9 /arch/arc/include/asm/irqflags-arcv2.h
parentARCv2: entry: document intr disable in hard isr (diff)
downloadlinux-107177b14d8179f864315fc4daed9da777ed30c2.tar.xz
linux-107177b14d8179f864315fc4daed9da777ed30c2.zip
ARCv2: intc: default all interrupts to priority 1
ARC HS Cores support configurable multiple interrupt priorities of upto 16 levels. In commit dec2b2849cfcc ("ARCv2: intc: Allow interruption by lowest priority interrupt") we switched to 15 which seems a bit excessive given that there would be rare hardware implementing so many preemption levels AND running Linux. It would seem that 2 levels will be more common so switch to 1 as the default priority level. This will be the "lower" priority level saving 0 for implementing NMI style support. This scheme also works in systems with more than 2 prioity levels as well. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/include/asm/irqflags-arcv2.h')
-rw-r--r--arch/arc/include/asm/irqflags-arcv2.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arc/include/asm/irqflags-arcv2.h b/arch/arc/include/asm/irqflags-arcv2.h
index e880dfa3fcd3..a64c447b0337 100644
--- a/arch/arc/include/asm/irqflags-arcv2.h
+++ b/arch/arc/include/asm/irqflags-arcv2.h
@@ -38,10 +38,10 @@
#define AUX_IRQ_ACT_BIT_U 31
/*
- * User space should be interruptable even by lowest prio interrupt
- * Safe even if actual interrupt priorities is fewer or even one
+ * Hardware supports 16 priorities (0 highest, 15 lowest)
+ * Linux by default runs at 1, priority 0 reserved for NMI style interrupts
*/
-#define ARCV2_IRQ_DEF_PRIO 15
+#define ARCV2_IRQ_DEF_PRIO 1
/* seed value for status register */
#define ISA_INIT_STATUS_BITS (STATUS_IE_MASK | STATUS_AD_MASK | \