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authorBjorn Helgaas <bhelgaas@google.com>2024-03-29 23:14:32 +0100
committerVineet Gupta <vgupta@kernel.org>2024-04-02 03:40:39 +0200
commitebfc2fd8873b4feb86f01835ad97282aede1e956 (patch)
tree8a117a03d68946d51b51045bb5490671906766a8 /arch/arc/include/asm/irqflags-compact.h
parentARC: mm: fix new code about cache aliasing (diff)
downloadlinux-ebfc2fd8873b4feb86f01835ad97282aede1e956.tar.xz
linux-ebfc2fd8873b4feb86f01835ad97282aede1e956.zip
ARC: Fix typos
Fix typos, most reported by "codespell arch/arc". Only touches comments, no code changes. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Vineet Gupta <vgupta@kernel.org>
Diffstat (limited to 'arch/arc/include/asm/irqflags-compact.h')
-rw-r--r--arch/arc/include/asm/irqflags-compact.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arc/include/asm/irqflags-compact.h b/arch/arc/include/asm/irqflags-compact.h
index 0d63e568d64c..936a2f21f315 100644
--- a/arch/arc/include/asm/irqflags-compact.h
+++ b/arch/arc/include/asm/irqflags-compact.h
@@ -46,7 +46,7 @@
* IRQ Control Macros
*
* All of them have "memory" clobber (compiler barrier) which is needed to
- * ensure that LD/ST requiring irq safetly (R-M-W when LLSC is not available)
+ * ensure that LD/ST requiring irq safety (R-M-W when LLSC is not available)
* are redone after IRQs are re-enabled (and gcc doesn't reuse stale register)
*
* Noted at the time of Abilis Timer List corruption