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authorVineet Gupta <vgupta@synopsys.com>2013-09-05 11:15:51 +0200
committerVineet Gupta <vgupta@synopsys.com>2013-11-06 06:11:38 +0100
commitd4599baf5c773660f32ee6bc35c1afab009a52d9 (patch)
treee7538e616f56ceade60bd63833df965afbcc50b0 /arch/arc/include
parentARC: cacheflush refactor #3: Unify the {d,i}cache flush leaf helpers (diff)
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ARC: cacheflush optim - PTAG can be loop invariant if V-P is const
Line op needs vaddr (indexing) and paddr (tag match). For page sized flushes (V-P const), each line op will need a different index, but the tag bits wil remain constant, hence paddr can be setup once outside the loop. This improves select LMBench numbers for Aliasing dcache where we have more "preventive" cache flushing. Processor, Processes - times in microseconds - smaller is better ------------------------------------------------------------------------------ Host OS Mhz null null open slct sig sig fork exec sh call I/O stat clos TCP inst hndl proc proc proc --------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 3.11-rc7- Linux 3.11.0- 80 4.66 8.88 69.7 112. 268. 8.60 28.0 3489 13.K 27.K # Non alias ARC700 3.11-rc7- Linux 3.11.0- 80 4.64 8.51 68.6 98.5 271. 8.58 28.1 4160 15.K 32.K # Aliasing 3.11-rc7- Linux 3.11.0- 80 4.64 8.51 69.8 99.4 270. 8.73 27.5 3880 15.K 31.K # PTAG loop Inv Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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