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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2021-09-05 20:43:03 +0200 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2021-09-05 20:43:03 +0200 |
| commit | e07af2626643293fa16df655979e7963250abc63 (patch) | |
| tree | 1889972d796e84f5b00ccc0c00c3615517bd340a /arch/arc/kernel/intc-compact.c | |
| parent | Merge tag 'riscv-for-linus-5.15-mw0' of git://git.kernel.org/pub/scm/linux/ke... (diff) | |
| parent | ARC: mm: vmalloc sync from kernel to user table to update PMD ... (diff) | |
| download | linux-e07af2626643293fa16df655979e7963250abc63.tar.xz linux-e07af2626643293fa16df655979e7963250abc63.zip | |
Merge tag 'arc-5.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC updates from Vineet Gupta:
"Finally a big pile of changes for ARC (atomics/mm). These are from our
internal arc64 tree, preparing mainline for eventual arc64 support.
I'm spreading them out to avoid tsunami of patches in one release.
- MM rework:
- Implement up to 4 paging levels
- Enable STRICT_MM_TYPECHECK
- switch pgtable_t back to 'struct page *'
- Atomics rework / implement relaxed accessors
- Retire legacy MMUv1,v2; ARC750 cores
- A few other build errors, typos"
* tag 'arc-5.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (33 commits)
ARC: mm: vmalloc sync from kernel to user table to update PMD ...
ARC: mm: support 4 levels of page tables
ARC: mm: support 3 levels of page tables
ARC: mm: switch to asm-generic/pgalloc.h
ARC: mm: switch pgtable_t back to struct page *
ARC: mm: hack to allow 2 level build with 4 level code
ARC: mm: disintegrate pgtable.h into levels and flags
ARC: mm: disintegrate mmu.h (arcv2 bits out)
ARC: mm: move MMU specific bits out of entry code ...
ARC: mm: move MMU specific bits out of ASID allocator
ARC: mm: non-functional code movement/cleanup
ARC: mm: pmd_populate* to use the canonical set_pmd (and drop pmd_set)
ARC: ioremap: use more commonly used PAGE_KERNEL based uncached flag
ARC: mm: Enable STRICT_MM_TYPECHECKS
ARC: mm: Fixes to allow STRICT_MM_TYPECHECKS
ARC: mm: move mmu/cache externs out to setup.h
ARC: mm: remove tlb paranoid code
ARC: mm: use SCRATCH_DATA0 register for caching pgdir in ARCv2 only
ARC: retire MMUv1 and MMUv2 support
ARC: retire ARC750 support
...
Diffstat (limited to 'arch/arc/kernel/intc-compact.c')
| -rw-r--r-- | arch/arc/kernel/intc-compact.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arc/kernel/intc-compact.c b/arch/arc/kernel/intc-compact.c index a86641b91e65..6885e422870e 100644 --- a/arch/arc/kernel/intc-compact.c +++ b/arch/arc/kernel/intc-compact.c @@ -142,7 +142,7 @@ IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ); * Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times. * Here local_irq_enable( ) shd not re-enable lower priority interrupts * -If called from soft-ISR, it must re-enable all interrupts - * soft ISR are low prioity jobs which can be very slow, thus all IRQs + * soft ISR are low priority jobs which can be very slow, thus all IRQs * must be enabled while they run. * Now hardware context wise we may still be in L2 ISR (not done rtie) * still we must re-enable both L1 and L2 IRQs |