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| author | Vineet Gupta <vgupta@synopsys.com> | 2013-06-17 11:03:15 +0200 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2013-06-27 11:07:57 +0200 |
| commit | dc81df244028e0d07c8723e3f7ebd1a35e848293 (patch) | |
| tree | 40aafc02150025631b15dc514469ff74318e71e6 /arch/arc/mm/cache_arc700.c | |
| parent | ARC: [tlb-miss] Extraneous PTE bit testing/setting (diff) | |
| download | linux-dc81df244028e0d07c8723e3f7ebd1a35e848293.tar.xz linux-dc81df244028e0d07c8723e3f7ebd1a35e848293.zip | |
ARC: [tlb-miss] Fix bug with CONFIG_ARC_DBG_TLB_MISS_COUNT
LOAD_FAULT_PTE macro is expected to set r2 with faulting vaddr.
However in case of CONFIG_ARC_DBG_TLB_MISS_COUNT, it was getting
clobbered with statistics collection code.
Fix latter by using a different register.
Note that only I-TLB Miss handler was potentially affected.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/mm/cache_arc700.c')
0 files changed, 0 insertions, 0 deletions