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| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | 2017-09-08 20:42:33 +0200 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2017-10-04 05:36:49 +0200 |
| commit | 6afa3bcf1f919c374d4606a7ed8078d3f67dfa90 (patch) | |
| tree | a092ec9d4e004b9e11ca97e67444ac0cb119e6e8 /arch/arc | |
| parent | ARC: [plat-axs103] Add temporary quirk to reset ethernet IP (diff) | |
| download | linux-6afa3bcf1f919c374d4606a7ed8078d3f67dfa90.tar.xz linux-6afa3bcf1f919c374d4606a7ed8078d3f67dfa90.zip | |
ARC: [plat-hsdk] sdio: Temporary fix of sdio ciu frequency
DW sdio controller has external ciu clock divider controlled via
register in SDIO IP. Due to its unexpected default value
(it should divide by 1 but it divides by 8)
SDIO IP uses wrong ciu clock and works unstable
So add temporary fix and change clock frequency from 100000000
to 12500000 Hz until we fix dw sdio driver itself.
Fixes SNPS STAR 9001204800
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc')
| -rw-r--r-- | arch/arc/boot/dts/hsdk.dts | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts/hsdk.dts index 229d13adbce4..daeef4ab2df9 100644 --- a/arch/arc/boot/dts/hsdk.dts +++ b/arch/arc/boot/dts/hsdk.dts @@ -120,7 +120,17 @@ mmcclk_ciu: mmcclk-ciu { compatible = "fixed-clock"; - clock-frequency = <100000000>; + /* + * DW sdio controller has external ciu clock divider + * controlled via register in SDIO IP. Due to its + * unexpected default value (it should devide by 1 + * but it devides by 8) SDIO IP uses wrong clock and + * works unstable (see STAR 9001204800) + * So add temporary fix and change clock frequency + * from 100000000 to 12500000 Hz until we fix dw sdio + * driver itself. + */ + clock-frequency = <12500000>; #clock-cells = <0>; }; |