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| author | Antoine Tenart <antoine.tenart@free-electrons.com> | 2017-03-29 11:38:27 +0200 |
|---|---|---|
| committer | Antoine Tenart <antoine.tenart@free-electrons.com> | 2017-04-03 09:06:55 +0200 |
| commit | ffdc394e1b4285f8b85663f44f1cbd43003523a7 (patch) | |
| tree | ac38491c02898fbb61ea6610eaeaf2f6f7f65898 /arch/arm/boot/dts/alpine.dtsi | |
| parent | ARM: dts: alpine: add spaces before the uart node units. (diff) | |
| download | linux-ffdc394e1b4285f8b85663f44f1cbd43003523a7.tar.xz linux-ffdc394e1b4285f8b85663f44f1cbd43003523a7.zip | |
ARM: dts: alpine: add valid clock-frequency values
Update the Alpine clock-frequency values with valid default values. The
bootloader can still update these values if needed, but at least we can
boot if it does not.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/alpine.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/alpine.dtsi | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi index d84bd7955b54..731df7a8c4e6 100644 --- a/arch/arm/boot/dts/alpine.dtsi +++ b/arch/arm/boot/dts/alpine.dtsi @@ -41,28 +41,28 @@ compatible = "arm,cortex-a15"; device_type = "cpu"; reg = <0>; - clock-frequency = <0>; /* Filled by loader */ + clock-frequency = <1700000000>; }; cpu@1 { compatible = "arm,cortex-a15"; device_type = "cpu"; reg = <1>; - clock-frequency = <0>; /* Filled by loader */ + clock-frequency = <1700000000>; }; cpu@2 { compatible = "arm,cortex-a15"; device_type = "cpu"; reg = <2>; - clock-frequency = <0>; /* Filled by loader */ + clock-frequency = <1700000000>; }; cpu@3 { compatible = "arm,cortex-a15"; device_type = "cpu"; reg = <3>; - clock-frequency = <0>; /* Filled by loader */ + clock-frequency = <1700000000>; }; }; @@ -81,7 +81,7 @@ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - clock-frequency = <0>; /* Filled by loader */ + clock-frequency = <50000000>; }; /* Interrupt Controller */ @@ -123,7 +123,7 @@ uart0: uart@fd883000 { compatible = "ns16550a"; reg = <0x0 0xfd883000 0x0 0x1000>; - clock-frequency = <0>; /* Filled by loader */ + clock-frequency = <375000000>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; @@ -132,7 +132,7 @@ uart1: uart@fd884000 { compatible = "ns16550a"; reg = <0x0 0xfd884000 0x0 0x1000>; - clock-frequency = <0>; /* Filled by loader */ + clock-frequency = <375000000>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; |