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authorFranklin S Cooper Jr <fcooper@ti.com>2017-07-26 04:15:50 +0200
committerTony Lindgren <tony@atomide.com>2017-08-14 20:34:24 +0200
commit7d8fec20913058812ae36f652a8ed07e4fba1420 (patch)
tree2cb461947bcd6c202fd79dfcffc099ce0b74eb9f /arch/arm/boot/dts/am335x-evm.dts
parentARM: dts: omap4-droid4: Add vibrator (diff)
downloadlinux-7d8fec20913058812ae36f652a8ed07e4fba1420.tar.xz
linux-7d8fec20913058812ae36f652a8ed07e4fba1420.zip
ARM: dts: am335x-evm: Enable NAND dma prefetch by default
Currently the default method of prefetch polled shows the highest possible read and write speed when minimal non NAND background activity is being done. But it is also very CPU intensive to reach these high speeds (CPU load of 99% via mtd performance tests). While DMA prefetch only uses 50% of the CPU to achieve around 23% less in top read and write performance. However, as the non NAND CPU load increases the read and write performance takes a large hit when using polled prefetch. Therefore, prefetch dma mode ends up outperforming prefetch polled in general "system level" test. So switch to using dma prefetch by default since it is likely what most users would prefer. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/am335x-evm.dts')
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 1c37a7c1ea17..ddd897556e03 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -531,6 +531,7 @@
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+ ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;