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| author | Tony Lindgren <tony@atomide.com> | 2014-10-30 01:16:47 +0100 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2014-10-30 16:35:17 +0100 |
| commit | e2c5eb78a3cc9b0d69ae924c33da50a4cd6d1fa4 (patch) | |
| tree | 099dcee356a550dcb0aeae1e8930b550a72ab0bf /arch/arm/boot/dts/am335x-igep0033.dtsi | |
| parent | ARM: dts: Fix bootloader version dependencies by muxing n900 smc91x pins (diff) | |
| download | linux-e2c5eb78a3cc9b0d69ae924c33da50a4cd6d1fa4.tar.xz linux-e2c5eb78a3cc9b0d69ae924c33da50a4cd6d1fa4.zip | |
ARM: dts: Fix wrong GPMC size mappings for omaps
The GPMC binding is obviously very confusing as the values
are all over the place. People seem to confuse the GPMC partition
size for the chip select, and the device IO size within the GPMC
partition easily.
The ranges entry contains the GPMC partition size. And the
reg entry contains the size of the IO registers of the
device connected to the GPMC.
Let's fix the issue according to the following table:
Device GPMC partition size Device IO size
connected in the ranges entry in the reg entry
NAND 0x01000000 (16MB) 4
16550 0x01000000 (16MB) 8
smc91x 0x01000000 (16MB) 0xf
smc911x 0x01000000 (16MB) 0xff
OneNAND 0x01000000 (16MB) 0x20000 (128KB)
16MB NOR 0x01000000 (16MB) 0x01000000 (16MB)
32MB NOR 0x02000000 (32MB) 0x02000000 (32MB)
64MB NOR 0x04000000 (64MB) 0x04000000 (64MB)
128MB NOR 0x08000000 (128MB) 0x08000000 (128MB)
256MB NOR 0x10000000 (256MB) 0x10000000 (256MB)
Let's also add comments to the fixed entries while at it.
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/am335x-igep0033.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/am335x-igep0033.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index a1a0cc5eb35c..c0e1135256cc 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -126,10 +126,10 @@ pinctrl-names = "default"; pinctrl-0 = <&nandflash_pins>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ nand-bus-width = <8>; ti,nand-ecc-opt = "bch8"; gpmc,device-width = <1>; |