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authorArun Siluvery <arun.siluvery@linux.intel.com>2015-06-19 19:37:13 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-06-23 14:01:41 +0200
commitc82435bbe5aca62fc54615ff8ba78134bfa33866 (patch)
treea15b8966a3f960af551c7c80128e043997fe949f /arch/arm/boot/dts/am335x-nano.dts
parentdrm/i915/gen8: Add WaDisableCtxRestoreArbitration workaround (diff)
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drm/i915/gen8: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround
In Indirect context w/a batch buffer, +WaFlushCoherentL3CacheLinesAtContextSwitch:bdw v2: Add LRI commands to set/reset bit that invalidates coherent lines, update WA to include programming restrictions and exclude CHV as it is not required (Ville) v3: Avoid unnecessary read when it can be done by reading register once (Chris). Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Dave Gordon <david.s.gordon@intel.com> Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'arch/arm/boot/dts/am335x-nano.dts')
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